LP-11 → LP-10 → LP-00 (hold ≥ 1 ms) → ULPS.
MIPI D-PHY 2.0 compliance tests include: mipi d phy 2.0 specification
(v2.0 improvement) – clock lane enters LP-11 when idle, reducing power. LP-11 → LP-10 → LP-00 (hold ≥ 1 ms) → ULPS